IBM explains its dual-ISA z/Architecture and Arm core design at Hot Chips 2026

IBM's Christian Zoellin and Christian Jacobi discuss a next-generation processor that supports both z/Architecture and Arm instruction sets at Hot Chips 2026.

Zoellin says separate decoders sit in a shared decode pipeline, while the caches, TLBs, and register files are reused, and endianness is handled in the load-store unit.

Jacobi explains that Arm support aims to bring its software ecosystem to mainframe workloads, and that Spyre's memory bandwidth needs grew as use cases shifted toward agentic AI.